NCVerilog - import VHDL into Verilog

Last Update: 2013/09/02 15:25+08

--- Intro ---

這篇是將 VHDL 導入到 Verilog 的方法
重點在interface(shell)的建立

環境: Linux - CentOS release 4.6 (Final)
Cadence tools: ncvhdl, ncvlog, ncelab, ncsim

--- Content ---

先用 VHDL 寫一個 not gate
inv.vhd

Library ieee;
use ieee.std_logic_1164.all;

entity inv is
  port( o: out std_logic;
        i: in std_logic);
end inv;

architecture proc of inv is
begin
  o <= not i; 
end;

然後 compile 它

ncvhdl inv.vhd

上述指令會建立 INCA_libs 資料夾
進去該資料夾底下, 執行下述 ncshell 指令
它會幫 entity inv => architecture proc 建立一個 interface(shell)
建好後 你可以在該目錄(INCA_libs) 找到一個 inv.vs (Verilog Shell) 的檔案
有興趣可以開起來看一下, 然後退回原本的目錄

cd INCA_libs
ncshell -import vhdl -into verilog inv:proc
cd ..

然後就可以在 verilog 中使用它了
test_bench.v

module test_bench;
 reg test_i;
 wire test_o;

 inv cell1(test_o, test_i);

 initial begin
  #5 test_i = 0;
  #1 $display("%b => %b", test_i, test_o);
  
  #5 test_i = 1;
  #1 $display("%b => %b", test_i, test_o);
  
  #5 test_i = 0;
  #1 $display("%b => %b", test_i, test_o);
  
  #5 test_i = 1;
  #1 $display("%b => %b", test_i, test_o);
 end
endmodule

不需要 include "inv.vs";
咱們把他編譯到 worklib 裡了
最後執行下述指令 看結果

ncvlog test_bench.v
ncelab test_bench:module
ncsim test_bench:module